"""
Copyright 2009, Thomas Dejanovic, Jay Shurtz.
 
This is free software; you can redistribute it and/or modify it
under the terms of the GNU Lesser General Public License as
published by the Free Software Foundation; either version 2.1 of
the License, or (at your option) any later version.

This software is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.

You should have received a copy of the GNU Lesser General Public
License along with this software; if not, write to the Free
Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
02110-1301 USA, or see the FSF site: http://www.fsf.org.

This class generates verilog HDL from the hatchling data structure.
"""
#---------------------------------------------------------------------

id = "$Id: verilog.py 667 2010-07-01 00:12:17Z jayshurtz $"
# $URL: http://hatch.googlecode.com/svn/tags/taggle_release_2.3/hatch/hatch_targets/verilog/obsolete/verilog.py $
# $Author: jayshurtz $
version = " ".join(id.split()[1:3])

#---------------------------------------------------------------------

from verilog_bus_factory import VerilogBusFactory

#---------------------------------------------------------------------

class Verilog:
    """ Base class for generation of verilog from a hatchling data structure.
    """

    def __init__(self, hatchNode, moduleName, tagetBus=None):
        """ hatchNode is a hatchling data structure.

            moduleName is the top level module name.

            targetBus is the target bus type for the generated verlog.
              If supplied it overrides the definition supplied as a
              property of the hatchling.
        """

        # make a bus object.
        vbf = VerilogBusFactory()
        vb = vbf.create(hatchNode, tagetBus)





# TODO - built-in-self-test 
if __name__ == "__main__":

    pass
